An electrostatic discharge, or ESD, is a transient discharge of static charge. A familiar example of an ESD is the spark that can occur between a person and a grounded object after the person walks across a carpet. The person acquires a static charge from the carpet; contact with the grounded object allows the static charge to discharge.
The energy associated with an ESD event can easily damage sensitive integrated circuit (IC) components. Protection circuits that can handle the high energies of ESD events are therefore integrated with sensitive IC components so that the protection circuitry can dissipate ESD energy. Typically, a voltage clamp limits the voltage on a selected external IC pin to a level that will not damage ESD-sensitive components. For a discussion of voltage clamps for ESD protection, see Ajith Amerasekera and Charvaka Duvvury, ESD in Silicon Integrated Circuits, pp. 30-52 (1995), and U.S. patent application Ser. No. 09/150,503, entitled "Electrostatic Discharge Protection Circuit," by Shahin Toutounchi and Sheau-Suey Li, filed Sep. 9, 1998. Both of these documents are incorporated herein by reference.
FIG. 1A is a schematic diagram of a conventional silicon-controlled rectifier (SCR) 100. SCRs are used extensively to protect ESD-sensitive components. SCR 100 is a two-terminal voltage clamp having an anode 102 and a cathode 104. SCR 100 responds to ESD events on anode 102 by sinking current to cathode 104, primarily via a pair of current paths: a PNP transistor 106 and a resistor 108 define the first current path; an NPN transistor 110 and a resistor 112 define the second. SCR 100 also includes a zener diode 114 connected between the bases of transistors 106 and 110. Zener diode 114 exhibits a reverse-bias breakdown voltage that is low relative to standard diodes. As described below, zener diode 114 acts as a trigger element to help turn on transistors 106 and 110 in response to ESD events on anode 102.
Anode 102 remains in some active voltage range relative to cathode 104 during normal circuit operation. In a typical logic circuit, for example, cathode 104 might be grounded (i.e., held at zero volts) and anode 102 might transition between zero and five volts or zero and 2.5 volts. Such differences in potential between anode 102 and cathode 104 are insufficient to turn on zener diode 114, so very little current passes through resistors 108 and 112. As a result, the voltages dropped across resistors 108 and 112 are normally insufficient to turn on respective transistors 110 and 106.
An ESD on anode 102 can raise the voltage between anode 102 and cathode 104 well above normal operating levels. Significant increases will exceed the break-down voltage of zener diode 114, causing zener diode 114 to conduct. The resulting voltages developed across resistors 108 and 112 will then turn on respective transistors 110 and 106, thereby sinking ESD current from anode 102 to cathode 104.
FIG. 1B is a graph of an illustrative I-V curve 116 for SCR 100 (FIG. 1A): the x-axis represents the voltage difference between anode 102 and cathode 104 (i.e., V.sub.A -V.sub.C) and the y-axis represents the current I.sub.scr through SCR 100 between anode 102 and cathode 104.
In the absence of an ESD (or some other over-voltage event), the anode voltage V.sub.A on anode 102 remains below the so-called "trigger" voltage V.sub.T required to turn on SCR 100. The current through SCR 100 therefore remains very low. When an ESD raises the anode voltage V.sub.A above trigger voltage V.sub.T, the anode voltage V.sub.A will "snap back" to a holding voltage V.sub.H. Once triggered, SCR 100 sinks current from anode 102 to cathode 104 until most of the energy of the ESD event is dissipated. The trigger voltage V.sub.T should be selected to ensure that SCR 100 triggers fast enough to avoid damaging any associated ESD-sensitive components (not shown).
Integrated circuits are becoming more complex as device engineers are able to pack more devices on each chip. These improvements are primarily due to advances in semiconductor processing technologies that afford the use of ever smaller circuit features. As features become smaller, reducing junction capacitance becomes increasingly critical to speed performance. One method of reducing junction capacitance involves the use of lower doping levels when forming substrates and well diffusions. Unfortunately, reducing doping levels complicates the task of providing adequate ESD protection.
ESD protection circuits typically include triggering mechanisms that depend upon the breakdown voltage of a selected junction. In general, the breakdown voltage of a given junction is inversely related to doping level. That is, lower doping levels provide higher breakdown voltages. The low well and substrate doping levels preferred for circuits with very small features can increase the breakdown voltage of ESD trigger mechanisms to unacceptably high levels. In modern 0.18-micron processes, the breakdown voltage of trigger mechanisms can approach the breakdown voltage of gate oxides. Consequently, an ESD-protection circuit can fail to trigger in response to an ESD event in time to avoid irreversibly damaging a neighboring gate oxide.
FIG. 1C is a cross-sectional diagram of an example of SCR 100 that addresses the problem of providing an adequate trigger mechanism for circuits with very small feature sizes. SCR 100 is formed on a p-type silicon substrate 118 using a conventional CMOS process. SCR 100 includes a number of diffusion regions, some of which are isolated from others by isolation regions 120. Isolation regions 120 are typically silicon dioxide formed using a conventional isoplanar isolation scheme. The diffusion regions include p+ regions 122, 124, and 126, n+ regions 128, 130, and 132, and an n-region 136. Of these, p+ diffusion 126 is formed within an n-well 134. A layer of silicide is divided into areas 138 that conventionally establish low-impedance electrical contact to the diffusion regions.
The various components of FIG. 1A are instantiated in substrate 118 as shown. For example, zener diode 114 is formed laterally between diffusion regions 124 and 130. A salicide block 140 prevents the zener junction formed between n- diffusion 136 and p+ diffusion 124 from shorting. Salicide block 140 is typically silicon dioxide. The break-down voltage of zener diode 114, and therefore the trigger voltage V.sub.T of SCR 100, depends primarily on the doping concentration of n- diffusion 136.
Instantiating zener diode 114 laterally, as depicted in FIG. 1C, allows process engineers a degree of flexibility in establishing the breakdown voltage of zener diode 114. The breakdown voltage of zener diode 114 can be adjusted by selecting an appropriate dopant dose for n- diffusion 136. Silicide block 140, typically silicon dioxide, then prevents zener diode 114 from shorting upon the formation of silicide layer 138. Unfortunately, the silicide blocking process is expensive and time consuming. Further, residual oxides from the formation of silicide block 140 can contaminate the subsequently formed silicide layers 138, and consequently increase their resistance. Finally, providing a sufficiently low breakdown voltage for zener diode 114 can be difficult for very dense ICs due to the use of reduced doping levels. There is therefore a need for an improved ESD protection circuit that works well in circuits with very small features and that does not require a silicide blocking process.